In the manufacture of, e.g., an FPD (Flat Panel Display), a circuit pattern is formed through a so-called photolithography process. In this photolithography process, as disclosed in JP2007-158253A, a specified film is formed on a target substrate such as a glass substrate and, subsequently, photoresist (hereinafter referred to as “resist”) is applied to form a resist film (or a photosensitive film). Then, the resist film is exposed in conformity with a circuit pattern and is developed to form the circuit pattern.
In the photolithography process, as shown in FIG. 19A, a resist pattern R may be made to have different thickness portions (namely, thick portions R1 and a thin portion R2, for example, having nearly half the thickness of the thick portions R1) and then may be subjected to etching more than once. This makes it possible to reduce the number of photomasks and the number of processing steps. Typically, the resist pattern R of this type can be obtained by half (halftone) exposure processing that makes use of a single halftone mask having different light transmittance portions.
A circuit pattern forming process using the resist pattern R applied with the half exposure processing will be described in detail with reference to FIGS. 19A through 19E. Referring to FIG. 19A, a gate electrode 200, an insulating layer 201, a Si layer 202 composed of an a-Si layer (undoped amorphous Si layer) 202a and an n+a-Si layer (phosphor-doped amorphous Si layer) 202b, and a metal layer 203 for formation of electrodes are sequentially arranged on a glass substrate G. A resist pattern R obtained by the half exposure processing and the development processing is formed on the metal layer 203.
After forming the resist pattern R (having the thick portions R1 and the thin portion R2), the metal layer 203 is subjected to etching (first etching), as shown in FIG. 19B, at which time the resist pattern R is used as a mask. Then, the resist pattern R as a whole is subjected to ashing under the presence of plasma. This produces resist patterns R3 having a nearly halved thickness, as shown in FIG. 19C (for example, the thicknesses of the thick portions R1 are nearly halved while the thin portion R2 may be removed to expose an underling portion of the metal layer 203). Subsequently, as shown in FIG. 19D, the exposed portion of the metal layer 203 and the exposed portion of the Si layer 202 are subjected to etching (second etching), at which time the resist patterns R3 are used as masks. Finally, as shown in FIG. 19E, a circuit pattern is obtained by removing the resist patterns R3.
In the half exposure processing using the resist pattern R having the thick portions R1 and the thin portion R2, however, the thickness of the resist pattern R may become uneven through the substrate plane during formation of the resist pattern R. This poses a problem in that the line width of the resultant patterns and the pitch between the resultant patterns become irregular.
In this regard, description will be made in more detail with reference to FIGS. 20A through 20E. FIG. 20A shows an instance where the resist pattern R is formed such that the thickness t2 of the thin portion R2 of the resist pattern R becomes greater than the thickness t1 of the thin portion R2 shown in FIG. 19A. In this instance, just like the process shown in FIGS. 19A through 19E, the metal layer 203 is subjected to etching (see FIG. 20B) and the resist pattern R as a whole is subjected to ashing (see FIG. 20C).
This produces resist patterns R3 having a nearly halved thickness as shown in FIG. 20C. Assuming that the thickness of the resist film removed is equal to that shown in FIG. 19C, the pitch p2 between the resist patterns R3 may become smaller than the pitch p1 shown in FIG. 19C. In this state, the metal layer 203 and the Si layer 202 are subjected to etching (see FIG. 20D) and the resist patterns R3 are removed (see FIG. 20E). Consequently, the pitch p2 of the circuit pattern thus produced becomes smaller than the pitch p1 shown in FIG. 19E (in other word, the line width of the circuit pattern becomes greater).